Delay Locked Loop (DLL) circuits are used to generate one or more output clock signals with alternate signal edges from an input clock signal. DLL circuits are commonly used to provide high-frequency clock signals to support storage devices, such as Double Data Rate (DDR) memories. DLL circuits are also commonly used in serial interfaces such as in networking components.
A conventional DLL circuit of interest includes an array of identical delay elements, a phase comparator and a tap selector. The array of delay elements includes M rows (e.g., M=4) and N columns (e.g., N=64) of delay elements. The delay elements are configured such that the delay elements can be set to form an adjustable delay chain. The adjustable delay chain of delay elements allow an input clock signal to be routed through selected delay elements to produce output signals that are phase-shifted by predefined degrees at different locations along the delay chain. The delay chain is adjusted by the tap selector, which can set the delay elements on a particular column to a return state so that the input clock signal circumvents the delay elements that are positioned beyond this column. Thus, the delay chain can be shortened or extended by selecting a different column of delay elements. In order to determine the correct length for the delay chain, the tap selector adjusts the delay chain by sequentially applying different combination of tap signals to the columns of delay elements. Each combination of applied tap signals sets the delay elements of a particular column to the return state. When the proper or “locked” combination of tap signals is applied to the columns of delay elements, the correct phase-shifted output signals are produced. This locked combination of tap signals is determined using the phase comparator, which compares the phase of the input clock signal with the phase of the output signal that is to be phase-shifted by 360 degrees as the tap selector applies different combination of tap signals to the columns of delay elements. The “locked” combination of tap signals is found when the phase of the input clock signal is synchronized with the phase of the compared output signal.
A concern with the conventional DLL circuit is that the delay elements cannot be tested to determine whether any of the delay elements has malfunctioned, e.g., stuck-at fault. Similarly, the tap selector cannot be tested to determine whether any of the tap selection signals are stuck at a particular state.
In view of these concerns, there is a need for a DLL circuit and method for testing the circuit to detect malfunctioned delay elements and malfunctioned tap selector.